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Ever since I built my 4 bay 3.5″ NAS using the Raspberry Pi which was placed inside a Netgear NV NAS enclosure, I’ve been wanting to make a single bay NAS with a 2.5″ drive to use as a small file server or for backups. I’ve decided that I’ll use it for remote backups in which I’ll use rsync over SSH from my linux server to backup some of my data at night.

(sneak peak)

Due to my use case, I’ll need to have it operating 24×7 and don’t really have a need for an LCD or even power button, so it will be a minimalistic design. The Raspberry Pi was purchased from Element14 / Newark and this time it has mounting holes which will make things more easier for us. In terms for the power supply, I’m able to re-use an existing 5V 2A supply but otherwise I could have used my SMPS.

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The SATA to USB adapter that I bought from Ebay was larger than I wanted so it’s time to make it smaller.

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I went ahead, opened it up, shortened the USB cables, separated the power cable out (as I don’t want the Pi itself to power it), re-soldered the wires to a USB connector I had – it’s now more compact. As a side effect, this SATA adapter has quite a bright blue LED which illuminates through the acrylic case which gives it some colour. Just using a spare 500GB hard drive whilst testing.

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Today we’ll be taking a look at the  D-Link DSL-200 ADSL USB Modem device which is the first ADSL modem I had back when we got ADSL in 2002, it’s a USB powered modem. The date code is 2002/27th week.

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The top and bottom board have quite a bit of inductors, the top right side of the board has quite a few capacitor all bunched together and we’ve got a fair amount of chips. We have a On Semi 51031 SMPS with a IRF7416 P mosfet to form part of the SMPS and there’s a 5171E boost regulator likely to be for the ADSL side (in the middle of the board).

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From our last post we looked at adding a transistor to the MC34063 and eventually changed to a P mosfet although we had to use a pretty large heatsink to dissipate all the heat. I decided to revist this SMPS to see if we could improve it to generate less heat, as I might have a few projects that could possibly use 5V output and 12V+ input.

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I decided to build the circuit with a NPN transistor – the TIP31 however with a small heatsink with 5V @ 0.37A, it rose up to 55C so I went back to a P mosfet. I began changing all the other parts – using different diodes, inductors, resistors however the P mosfet still got pretty hot even with a small heatsink.

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Thinking that the MC34063 could be causing the issues itself, I went ahead and used an ATtiny to replicate what a little bit of SMPS would be doing – pulsing an output high and low for a specific duty cycle until I reached 5V. The heat was about the same as the MC34063 but just a little less as I didn’t compensate for the load reducing the voltage.

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So it’s back to the IRF9540 P mosfet, after researching into it, it seems like the turn off time / capacitance is pretty important for our application, this mosfet has 1400pF input / 590pF output capacitance, 73ns rise time, 34ns turn off and 57ns fall time. On paper this mosfet seems good however as above we can see the turn off time is really 4us (yellow line, going low to high). Also there is an spike (blue) which I was able to soften down later a bit by adding a 470uF capacitor to the input VCC/GND (before I had 100uF).

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Today we’ll be taking a look at the IBM Server Redundant Power System (2006) board which was taken out of an IBM server, its purpose is to combine both power supplies into one and know when a power supply goes offline/online. The date code is 2006/46th week.

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I was able to take both power supplies from the server which were rated at 12V at 69A which gives 828 watts which is unusual to have that much amps on the 12V rail and I would like to use each one independently of this RPS board which we’ll also look at.

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It’s a nice looking board and there are two sub-boards for the power supplies, all that’s being carried over is 12V on the thick red wires and some control lines too. We’ve got a little sub-board soldered on the main board too with two chips, some capacitors and an inductor, likely to be a SMPS. Another component that stands out is the TO220 part tipped horizontally to keep it low profile, usually you don’t see the metal part in the air like that. They’ve got a Infineon 04N03LA N power transistor and current sense resistor for the 5x 12V rails to regulate how much current each rail receives.

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From our previous post, we made our prototyped PCBs which all worked together well. This time we just have a quick update – we’re making a few changes along with building acrylic cases/mounts for some of our boards.

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I’ve been rethinking my idea about using the existing plastic casing for the PIR, since I intended this to be a standalone alarm system I should really make my own case. We’ll need a way to mount the PIR sensor at an angle to the wall to point a bit downwards otherwise it’ll just point straight on and may not cover the whole room. Initially I started with the design above, there’s quite a bit of acrylic boards all screwed together with M2 screws.

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I went for a re-design and now it’s looking better with less parts being used. I’ll need to add some mounts to the ATtiny84 PIR PCB, switch the M3 screws that hold the Lipo in place with longer M2 screws and then add a small hole at the top so I can nail the bottom board to the wall and that will sort out the PIRs.

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Today we’ll be taking a look at the  Softlog Systems Faxlog 4 device which as it says converts incoming faxes to serial and then there’s another box which plugs into the PC. The date code is 2006/34th week.

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There was a RJ45 cable connecting this sub-board to the main board, whether or not this was all the parts in the Faxlog system is unknown. There is also a selectable address line via DIP switches.

Main Board

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The PCB has a lot more ICs and components than I had expected. We’ve got some phone line filtering and protection with some larger than normal capacitors (compared to internet routers), along with 2 TIP31CG NPN transistors, some RY5W-K relays, a NMV0515SC DC-DC converter 5V input to 15V output and some P2769100SMD transformers. Coming from the transformers / opto-isolators, we’ve got 3 UA741 opamps and 2 DG419 analog switches. In terms of power supply side, it’s 9V input with a large 1000uF capacitor, LM2940CT 5V LDO with heatsink and a NMA0505DC 5V input to -5 and +5V output.

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Ever since I did a teardown of the Squeezebox I wanted to re-use the Vacuum fluorescent display which is a MN32032A. It’s running off a 55V power supply, I was able to identify the data lines and by using my 8 channel logic analyser I took a few samples of the data.

Here’s the end result, it works to some degree, as you can see there is some signs of random pixels  lighting up which I’ll need to look into at a later stage.

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The VFD seems easy enough to use, it’s serial based where you shift out 336 bits containing 32 rows (32 bytes) and 80 grids (10 bytes) but we have to note that when we shift out each row byte it isn’t in the order of abcdefgh but rather ahbhcdfe and that each grid has controls only 4 lights per row. For example, if you were to turn on row 1 and turned on all the grids, a straight line would appear across the screen.

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What we’re required to do is shift out 336 bits of which we need to turn on 2 grids at a time, latch the data and cycle GCP. If you do encounter ghosting you can turn the blanking (BLK) high for one time period and then low (however doing this didn’t help the problem I had). I’m not sure as to what the GCP line does but without it the display doesn’t work, it could mean grid control pulse?

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From our last part we made some prototype boards including the buffer board and fixed the reading issues. In this part we’ll look at the software side to display the data we extract, add trigger options/sample rates, some hardware changes and possible design changes which could give us an 100MHz logic analyser.

Software for displaying our data

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I had a look around at some software options that would just work out of the box and settled with one called MiniLA, they also had made an 100MHz logic analyser – it’s a beefier version of what I’m trying to achieve,  their one has 32 channels and the CPLD/SRAM alone would cost $25-35 (about $40-50 in Australia) where as I’d like to make a small 8 channel one with USB (and it’s a learning experience for me too).

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After looking around at the file format, it’s similar to how I was sending my data, so I was able to figure out how the data was formed – 00 00 FF 00 would set channel 1 to 8 all high for one time period. From the picture above, to change the time scale units from us to ns, you can change 41 to 42 and to change the time scale total length from say 2.52 to 2.62 ms you’d change 87 to 88. This should give us the flexibility to change time scale units depending on the clock we select.

Trigger/sample options

As the ATmega will act as the trigger source, I’ve been able to add options such as choosing which pin to trigger on, trigger level – high or low, trigger delay, trigger count – how many triggers we should wait for, sample rate and number of samples.

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Today we’ll be taking a look at the  D-Link AirPlus Xtreme G Wireless Router  – a 4 port 10/100 ethernet and wireless router with 1 external antenna which has a date code of 2005/15th week.

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Two screws later and we’re in.

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At first glance the PCB is quite big and there’s a bit of empty space on it, they could have made it smaller if they really wanted to. We’ve got 4 chips plus a Wifi chip underneath the metal shield, an MPS MP1410ES SMPS on the input which can accept 5V to 15V, an ADE435 voltage regular near the metal shield and we have two AME AME8807 LDOs. Also we’ve got some tantalum capacitors which haven’t been too common in the routers I’ve seen.

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From our last part we were able to read the data from the SRAM using an ATmega but found that we couldn’t run the SRAM with a 100MHz clock and when reading the data out it was noisy/inaccurate – even re-reading the same address ranges would give different results. In this part, I’ve made some prototype boards and we’ll look into fixing the reading issues.

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I decided to make a new board for the CPLD so I could mount it and the SRAM to a main board and also made a buffer logic board to be mounted under the main board plus there is also a very small board for the 50MHz oscillator.

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For the buffer board, I’m using 2x 74LVC125 each one does 4 inputs. What I didn’t realise is that these are active low so I’ve modified my CPLD code to suit: CPLD_LogicAnalyser_v0.2

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