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From our last part we made some prototype boards including the buffer board and fixed the reading issues. In this part we’ll look at the software side to display the data we extract, add trigger options/sample rates, some hardware changes and possible design changes which could give us an 100MHz logic analyser.

Software for displaying our data

la6-1

I had a look around at some software options that would just work out of the box and settled with one called MiniLA, they also had made an 100MHz logic analyser – it’s a beefier version of what I’m trying to achieve,  their one has 32 channels and the CPLD/SRAM alone would cost $25-35 (about $40-50 in Australia) where as I’d like to make a small 8 channel one with USB (and it’s a learning experience for me too).

la6-2

After looking around at the file format, it’s similar to how I was sending my data, so I was able to figure out how the data was formed – 00 00 FF 00 would set channel 1 to 8 all high for one time period. From the picture above, to change the time scale units from us to ns, you can change 41 to 42 and to change the time scale total length from say 2.52 to 2.62 ms you’d change 87 to 88. This should give us the flexibility to change time scale units depending on the clock we select.

Trigger/sample options

As the ATmega will act as the trigger source, I’ve been able to add options such as choosing which pin to trigger on, trigger level – high or low, trigger delay, trigger count – how many triggers we should wait for, sample rate and number of samples.

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Today we’ll be taking a look at the  D-Link AirPlus Xtreme G Wireless Router  – a 4 port 10/100 ethernet and wireless router with 1 external antenna which has a date code of 2005/15th week.

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Two screws later and we’re in.

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At first glance the PCB is quite big and there’s a bit of empty space on it, they could have made it smaller if they really wanted to. We’ve got 4 chips plus a Wifi chip underneath the metal shield, an MPS MP1410ES SMPS on the input which can accept 5V to 15V, an ADE435 voltage regular near the metal shield and we have two AME AME8807 LDOs. Also we’ve got some tantalum capacitors which haven’t been too common in the routers I’ve seen.

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From our last part we were able to read the data from the SRAM using an ATmega but found that we couldn’t run the SRAM with a 100MHz clock and when reading the data out it was noisy/inaccurate – even re-reading the same address ranges would give different results. In this part, I’ve made some prototype boards and we’ll look into fixing the reading issues.

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I decided to make a new board for the CPLD so I could mount it and the SRAM to a main board and also made a buffer logic board to be mounted under the main board plus there is also a very small board for the 50MHz oscillator.

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For the buffer board, I’m using 2x 74LVC125 each one does 4 inputs. What I didn’t realise is that these are active low so I’ve modified my CPLD code to suit: CPLD_LogicAnalyser_v0.2

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Today we’ll be taking a quick look at the Netcomm NB5 ADSL2+ Modem Router which has a date code of 2005/33rd week and a Ethernet/USB based modem/router. We’ve done a teardown of the NB5 ADSL version of this router before so lets how similar they are.

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Some screws later and we’re in.

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There are a few noticeable parts on the board, firstly the 3300uF 16V capacitor glued to the board (which has come off), a larger than usual 100uH inductor, a fuse with a metallic outer shell and they are using an MC34063 SMPS.

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From our last part we chose the switches to use, the cabling idea to use network cables to connect to USB cables, the 7402 NOR gate to switch between inputs and gave it a test run on the VGA which worked. In this part we’ll put it all together and think about how we can add more input ports to do a 4, 8, 16 port KVM.

(sneak peak of KVM)

The first thing I did was test the 7402 NOR gate to see if there is an oscillation at startup, after a few attempts I found no issues but that you should tie unused gates to ground; even if it started in an unknown state, the state doesn’t change so it’s not too much of a concern for me.

IMG_3551 IMG_3553

I decided to have the VGA and USB boards separate as it would be easier to route them. The VGA board was built, there was a small mistake with choosing the wrong 7402 part in Eagle so I had to make a few modifications and it tested ok, there is a 6 pin header near the center to connect to the USB board.

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Today we’ll be taking a quick look at the SMC 2-Port Annex A ADSL2/2+ Modem Router (SMC7901BRA2) which has a date code of 2008/4th week and it’s a simple Ethernet or USB based modem/router.

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Two screws later and we’re in.

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The first thing noticeable is the large Elcon 3300uF 25V capacitor near the middle of the board. There is a 6×2 pin header which is most likely a Jtag header, 2 crystals 35.3MHz and 25MHz and we have a Semitech SC4519H SMPS.

The main chip is an Infineon PSB7200ZDW XWAY AR7 with an ISSI IS42S16800A 128Mb SDRAM and an Eon EN29LV160AB-70TCP 16Mb Flash.

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Raspberry Pi Single Bay NAS Preview

Ever since I built a Raspberry Pi 4-bay NAS in an existing Netgear NAS case I’ve been wanting to make a smaller custom acrylic version with just a 2.5” 750GB hard drive for either backups (like a small Synology) or a fileserver overall it should end up being quite small.

rpi-512 wipi

The main components of this project will be the Rapsberry Pi and Wi-pi adapter which I bought it from Element14 / Newark. Using the the Wi-Pi adapter I could make it all wireless.

Like my last NAS, I’ll be adding in a 16×2 LCD display to show the status, as I’ll be using a 2.5” drive all I’d need is a 5V 2-3A power adapter and a USB to SATA adapter of which I’ve found a better adapter that should be easier to plug the drive easier.

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From our last part we switched tested the Cypress 1Mbit SRAM and read the data out with an Olimex STM32 board. In this part we’ll move to an ATmega to read out the data and use it for triggering the CPLD which will be continually sampling the inputs – the reason is because the ATmega runs slower than the CPLD so a few clock cycles will occur from when it detects the trigger to when it signals the CPLD.

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CPLD Side

On the CPLD we can remove the data pins which were being used to test the SRAM and we can link WE and OE pins directly to the SRAM. We’ll re-use the writing pin to tell the CPLD to start capturing data or to be in the read mode, another pin for when we want it to trigger and it records the address minus 50 so that we can see some data before the trigger event.

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From our last part we switched to the EPM3064 CPLD for our logic analyser. In this part we’ll use the Cypress 1Mbit SRAM to store the data that we capture.

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It’s a parallel SRAM which can run at 100MHz which allows us to save time compared to a regular 8 pin SRAM as we don’t have to clock in the address and clock in the data. All we have to do now is set the address pins, feed in the data and set the CE/WE pins low, the perfect job for a CPLD.

cpld3-2

Writing and reading to the SRAM is fairly easy – to write we pull CE and WE low and to read we pull CE and WE low. In all other states the outputs are in high impendance, this allows us the option of adding more SRAM chips.

In order to test out the SRAM and the clock feed to the CPLD, I’ll have the CPLD increment an 8bit number which will be written to the SRAM and then read out with an MCU.

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Today we’ll be looking into something a bit different than the regular items we have on – the Slim Devices Squeezebox v3 Network Music Player which has a date code of 2006/12th week. The Squeezebox is a LAN/Wifi network music player which plays music from your computer and outputs it to RCA, S/PDIF or headphones.

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It can also play internet radio and also doubles as an RSS news ticker. The screen is a VFD which looks very nice, maybe I can use it for a project.

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Looks like we have an IR sensor at the front, on the back we have the Wifi board with two antennas and some chips. We’ve got a large 3300uF 16V capacitor though it’s a Samxon branded one. There is another board underneath with all the processing power which we’ll look afterwards.

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