module SPI (SI, CS);
  
//input CLK;
reg CLK;
//reg ENABLE;
reg [2:0] CNT; // Counter for counting to 8 
reg [15:0] ADDRESS; // Address
reg [3:0] COUNTER;
reg [7:0] DATA; // Data to write
reg [2:0] STATE; // State, 1 = Write Instruction, 2 + 3 = 16 bit Address, 4 = Byte to write

output SI; // Data to sram
reg SI;
output CS; // Chip select
reg CS;
//output BUSY;
reg [5:0] BUSY;

initial CNT = 1'b0;
initial STATE = 1'b0;
initial SI = 1'b1;
initial ADDRESS = 16'b0110001110001110;
initial COUNTER = 4'd15;
initial DATA = 8'b10101010;
initial CS = 1'b1;
initial BUSY = 6'b000000;
  
always @ (posedge CLK)
begin
  if (BUSY == 62) begin
  //if (ENABLE == 1) begin
    //BUSY = 1'b1;
    CNT = CNT + 1;
    
    if (STATE == 0) begin
      CS = 1'b0;
      CNT = 3'd7;
      STATE = STATE + 1;
      //BUSY = 1'b1;
      SI = 1'b0;
    end  
    else if (STATE == 1) begin // Write Instruction
      if (CNT == 0) SI = 1'b0;
      if (CNT == 6) SI = 1'b1;
      if (CNT == 7) begin
        SI = 1'b0;
        STATE = STATE + 1;
      end
    end
    else if (STATE == 2) begin // 16 bit Address 
       SI = ADDRESS[COUNTER];
       COUNTER = COUNTER - 1;
       if (COUNTER == 15) begin
         STATE = STATE + 1;
         COUNTER = 7; // Re-assign address count to data counter
       end
    end  
    else if (STATE == 3) begin
      SI = DATA[COUNTER];
      COUNTER = COUNTER - 1;
      if (CNT == 7) begin
         STATE = STATE + 1;
      end
    end      
    else if (STATE == 4) begin
       SI = 1'b1;
       CS = 1'b1;
       STATE = 1'b0;
       //BUSY = 1'b0;
       BUSY = BUSY + 1'b1;
    end 
    else STATE = STATE + 1'b1;
  end
  if (BUSY < 62) begin
    BUSY = BUSY + 1'b1;
  end
end


initial
begin
   CLK = 1'b0;
   forever #5 CLK = ~CLK;
end

//initial
//begin
 // ENABLE = 1'b0;
 // forever #500 ENABLE = ~ENABLE;
//end

endmodule