module sram (CLKin,
RESET,
LED, 
IN1, IN2, IN3, IN4, OUT1, OUT2, OUT3, OUT4, 
SI_IN, SI_OUT, SO_IN, SO_OUT, CS_IN, CS_OUT, SCK_IN, SCK_OUT);

reg [3:0] CYCLECOUNT; // Clock cycle for counting to 16
reg [1:0] UPDATECLK; // Used to divide the main clock

input CLKin;
input RESET;
output LED;
reg LED;

input IN1;
input IN2;
input IN3;
input IN4;
output OUT1;
reg OUT1;
output OUT2;
reg OUT2;
output OUT3;
reg OUT3;
output OUT4;
reg OUT4;

input SI_IN;
input SO_IN;
input CS_IN;
input SCK_IN;
output SI_OUT;
reg SI_OUT;
output SO_OUT;
reg SO_OUT;
output CS_OUT;
reg CS_OUT;
output SCK_OUT;
reg SCK_OUT;

always @ (posedge CLKin)
begin
  if (!RESET) begin
    CYCLECOUNT <= 4'd7;
    LED <= 1'b0;
    UPDATECLK <= 2'd2;
	 SI_OUT <= SI_IN;
	 SO_OUT <= SO_IN;
	 CS_OUT <= CS_IN;
	 SCK_OUT <= SCK_IN;
  end
  else begin
    // Divide the main clock by 4
    if (UPDATECLK == 1) begin
      SCK_OUT <= ~SCK_OUT;
      UPDATECLK <= 2;
    end
    else UPDATECLK <= UPDATECLK + 1'b1;
    
    // If we are in a clock low, then do everything here
    if (UPDATECLK == 3 && SCK_OUT == 0) begin
		  // Data
		  OUT1 <= IN1;
		  OUT2 <= IN2;
		  OUT3 <= IN3;
		  OUT4 <= IN4;
		  SI_OUT <= IN1;
		  
		  if (CYCLECOUNT == 7) LED <= 1'b0;
        if (CYCLECOUNT == 0) begin
           CYCLECOUNT <= 7;
           LED <= 1'b1;
        end
        else CYCLECOUNT <= CYCLECOUNT - 1'b1;
    end
  end
end
endmodule