module sram (reset, writing, readpulse, address, data, ce); reg clockin; input reset; input writing; input readpulse; reg [5:0] readincrement; output [16:0] address; reg [16:0] address; output [7:0] data; reg [7:0] data; output ce; wire ce; always @ (posedge clockin) begin if (!reset) begin address <= 17'b0; data <= 8'bz; readincrement <= 1'b0; end else begin if (writing) begin address <= address + 17'b1; data <= data + 8'b1; end else begin data <= 8'bz; if (readincrement == 1 && readpulse) begin address <= address + 17'b1; end readincrement <= readincrement + 1'b1; end end end assign ce = (reset) ? clockin : 1'b1; // For testing initial begin clockin = 1'b0; forever #5 clockin = ~clockin; end endmodule