module logicanalyser1 (clockin,
reset,
writing,
readpulse,
address,
data, 
ce);

input clockin;
input reset;
input writing;
input readpulse;

output [16:0] address;
reg [16:0] address;
inout [7:0] data;
reg [7:0] data;
reg readok;
output ce;
wire ce;

always @ (posedge clockin) begin
	if (!reset) begin
		address <= 17'b0;
		data <= 8'bz;
		readok <= 1'b0;
	end
	else begin
		if (writing) begin
			address <= address + 17'b1;
			data <= data + 8'b1;
		end
		else begin 
			data <= 8'bz;
			if (readpulse == 1 && readok == 0) begin
				readok <= 1'b1;
				address <= address + 17'b1;
			end
			if (readpulse == 0) begin
				readok <= 1'b0;
			end
		end
	end
end

assign ce = (reset) ? clockin : 1'b1;

endmodule