Feed on
Posts
Comments

From our last part we made some prototype boards including the buffer board and fixed the reading issues. In this part we’ll look at the software side to display the data we extract, add trigger options/sample rates, some hardware changes and possible design changes which could give us an 100MHz logic analyser.

Software for displaying our data

la6-1

I had a look around at some software options that would just work out of the box and settled with one called MiniLA, they also had made an 100MHz logic analyser – it’s a beefier version of what I’m trying to achieve,  their one has 32 channels and the CPLD/SRAM alone would cost $25-35 (about $40-50 in Australia) where as I’d like to make a small 8 channel one with USB (and it’s a learning experience for me too).

la6-2

After looking around at the file format, it’s similar to how I was sending my data, so I was able to figure out how the data was formed – 00 00 FF 00 would set channel 1 to 8 all high for one time period. From the picture above, to change the time scale units from us to ns, you can change 41 to 42 and to change the time scale total length from say 2.52 to 2.62 ms you’d change 87 to 88. This should give us the flexibility to change time scale units depending on the clock we select.

Trigger/sample options

As the ATmega will act as the trigger source, I’ve been able to add options such as choosing which pin to trigger on, trigger level – high or low, trigger delay, trigger count – how many triggers we should wait for, sample rate and number of samples.

For the sample rate, we can just switch between the analog switch and change the OCR0A timer 0 value to suit the clock rate we’d like, I’ve gone with these clock rates: 10/5/2.5/1MHz and 500/250/100KHz.

While we are waiting for a trigger, we turn on the capture LED, start reading the pins and then compare if the pins selected for triggering are high or low depending on our trigger level been high or low. We also check how many trigger counts we are waiting for too.

For the trigger delay, we setup timer 2 and can simply count the timer overflows to give us an approximate delay time – 78 overflows for each millisecond delay.

The sample rate can be changed and the end count is kept on the ATmega, when reading back the data once the end count is reached, we output an ‘x’ to indicate the end of data.

In the logic analyser extract program whenever we update any settings/capture/extract we always update the settings on the ATmega side, for some of the variables we add 1 here and on the ATmega side we minus 1, this is because if they read as 0 when sending, it would represent the end of the string.

Small hardware changes

For the buffer board after some testing, it’s very sensitive to the touch, so I’ve added 100K pull down resistors on the inputs to each buffer. Instead of using 2x quad buffers I’ll just use 1x octal buffer 74LVC244A.

I was planning on using an logic level converter for programming the ATmega in-circuit but really a quad buffer will be sufficient as we only care about converting 5V to 3.3V and not the other way around. At the moment I have a buffer with 1M pull up for the ATmega reset, when the programmer is connected it pulls this pin low.

Possible changes for a 100MHz logic analyser

la6-3

I’ve been thinking about how to re-achieve the 100MHz logic analyser which I had hoped of doing in the first place. If I went with the Altera EPM3032ATC44-4 32 macrocell CPLD which can operate at 227MHz and added on 2x SRAMs, I could potentially interleave the memory with a clock divider of 2 to give 20ns clock so one will be writing whilst the other would be waiting and then they’d switch. The Fmax summary reported is 200MHz so Fmax won’t affect us this time.

I would have to change the way the CPLD does capturing back to counting to 50 and if the start capture line is low, reset the count in order to fit it into the 32 macrocells. I have 2 pins spare and could use them to expand the SRAM from 1Mbit to 4Mbit but then I’ll need to see if I can modify/re-compile MiniLA to extend the end from 131K to 512K, it would allow for 10ms of capture at 100MHz with 2 SRAMs. It’s something to look into a do more testing, perhaps for another version.

Building a CPLD Based Logic Analyser – Part 1: SPI writing in Verilog, Testing the basics and modifying Scanalogic SCL files to insert our own data
Building a CPLD Based Logic Analyser – Part 2: Switching to the EPM3064 CPLD
Building a CPLD Based Logic Analyser – Part 3: Testing the Cypress 1Mbit SRAM
Building a CPLD Based Logic Analyser – Part 4: Reading data/triggering with an ATmega with V-USB and testing
Building a CPLD Based Logic Analyser – Part 5: Prototype boards and fixing reading issues
Building a CPLD Based Logic Analyser – Part 6: Software side, trigger/sampling options, hardware changes and possible changes for a 100MHz analyser
Building a CPLD Based Logic Analyser – Part 7: PCBs arrived, move to Sigrok Pulseview, simple GUI program and a few software modifications

Leave a Reply